The present invention relates to the communication of digital data, and more particularly to a method and apparatus for improving the apparent accuracy of a relatively inaccurate clock circuit used in a data receiver based on timing information contained in a received signal.
In digital communications, it is frequently necessary to extract a coherent clock signal from an input data stream. A phase lock loop (PLL) is often used for this task by locking a voltage controlled oscillator (VCO) to the input data. The output of the VCO is then used as a clock to extract the data bits from the input signal.
In a PLL, feedback is used to maintain an output signal in a specific phase relationship with a reference input signal. In clock recovery circuits, the output signal is derived from an adjustable master oscillator. Typically, it is required to provide a high precision adjustable master oscillator (i.e., clock) in order to quickly acquire a timing component (timebase) necessary to receive and recover a desired signal. The timing component may be embedded in data packets containing the specific information that is desired to be received.
In systems in which video, audio or other data transport services are provided asynchronously with respect to the data transfer rate of the communication system, it is necessary to synchronize the local output clock (i.e., the receiver master clock) to timing information embedded in the incoming packet data. Often, the nominal timebase frequency of the packet services are very close to a known frequency, such as on the order of a few parts per million (ppm), but are still not synchronous. In order to synchronize the local output clock to the timing information embedded in the incoming packet data, a packet time reference tracking loop (i e., "output timing loop") is used to control the master clock based on the difference between the master clock frequency and the phase and timing information present in the received packets.
It is typical for the bandwidth of the output timing loop to be quite narrow, for example on the order of much less than one Hz. As a result of this low loop bandwidth, the local output oscillator can require a significant amount of time to acquire a desired signal. An approach to ameliorating this problem, as indicated above, has been to maintain a high precision local master clock frequency. For example, master clocks having an accuracy on the order of a few ppm are appropriate. The requirement for an accurate master clock introduces complexity and significant cost into data receiver systems.
It would be advantageous to provide a data receiver that can quickly acquire a desired timing signal using a low cost local master clock. It would be further advantageous to provide such a system that increases the apparent accuracy of a less accurate clock in order to reduce the amount of time necessary to acquire a desired signal.
The present invention provides a method and apparatus enjoying the aforementioned advantages for improving the apparent accuracy of a clock circuit used to recover transmitted information signals in a data receiver.